1. Field of the Invention
The present invention relates to a timing unit implemented with TTL technology for use with data processing systems utilizing fast microprocessors.
2. Description of the Prior Art
It is known that particularly fast integrated microprocessors have been recently made available to the market. They operate on the basis of high frequency timing cycles.
The Motorola 68020 microprocessor, for example, can operate with a clock rate of 16.66 MHz and units operating at 20 MHz will soon be marketed.
These microprocessors used in conjunction with a few external components and peripheral units, memories, input/output data units and peripheral controllers may constitute complete data processing systems.
In such systems in order to exploit the full potential and speed of said microprocessors it is necessary to make use of fast memories with a read/write cycle time comparable to the execution time required by the microprocessors to carry out a memory data read/write operation.
Typically to execute a memory read operation the 68020 microprocessor requires 3 clock cycles; that is, 180 nsec. at the 16.66 MHz clock rate.
These cycles consist of 6 successive phases, S0, S1, S2, S3, S4, S5 in which the timing signal is alternatively at logic level "1" and "0".
As the memory address is made available by the microprocessor within the first half clock cycle (phase S0) and the read out data must be available in the first half of the third clock cycle (within phase S4), it is necessary that the memory read cycle, from the time when the memory is addressed to the time when the read out data is available, does not exceed 90 nsec.
In order to be able to use memories that do not operate at such a speed, the 68020 microprocessor (and others similar to it) is provided with an interval arrangement that allows wait cycles to be inserted.
The availability of the read data within a certain period of time must be "preannounced" to the microprocessor through the activation of a DTACK signal at logic level "0" by an external memory management unit (MMU).
If this signal is activated during phase S2 the microprocessor loads the data read from memory into an interface register at the beginning of phase S5 and the read operation is completed in three subsequent clock cycles.
If signal DTACK is not asserted during phase S2 the microprocessor enters a wait state for a clock cycle.
If the DTACK signal is received during the wait cycle the microprocessor resumes operation and completes the read operations in three successive phases S3, S4, S5; that is, the read operation is carried out in 4 clock cycles.
If the DTACK signal is not asserted even during the wait cycle the microprocessor remains in the wait state during further timing cycles.
It is obvious that under those conditions a considerable decrease in performance takes place.
Therefore the use of fast memories and architectures allowing information to be transferred between microprocessor and memory without appreciable delay times is essential.
In spite of these contrivances, it may, however, happen that the memory read cycle exceeds the desirable time for just a few nanoseconds, which causes the insertion of wait cycles whose duration is equal to 60 nsec. or more and a performance decrease that is disproportionate to the actual requirements.
The best of the knowledge available so far on the matter, can be found in the article "Verkurzter WAIT-Zyklus beschleunight 68000 Systeme" published in the magazine "Electronik" No. 3, Oct. 2, 1984, on pages 59-60. This article describes a circuit used for selectively generating wait states with a duration of only 1/2 and not 1/4 of the clock cycle. Furthermore a frequency divider unit, activated by a clock generator has a feedback loop which comprises a frequency divider flip flop and a NAND gate in series.
The frequency operation is therefore limited by the sum of the following propagation delay times:
(a) delay time of flip flop with respect to the clock, PA1 (b) delay time of signal in the NAND gate, PA1 (c) set-up time of input signal to flip flop.
Even greater is the restriction introduced by the control network for the insertion of wait states, which comprises a loop which, besides the flip flop and the previously mentioned NAND gate includes a further NAND gate.
Another drawback of the circuit described in the above-mentioned article is that it uses an (AS) signal generated by the microprocessor to generate a wait state to stop the timing unit; whereas the restart of the timing unit is determined by the (DTACK) signal generated by the memory.
This is an extremely risky approach because in case of no answer from the memory a "dead lock" occurs; that is, a system unrecoverable halt condition arises.
In addition, the described circuit can lengthen the cycle time by 1/2 only in phase S2; whereas it would be useful to have timing units that allow cycle times to be lengthened also in the successive phases such as, for instance, phase S3 or s4.
In fact the activation of the DTACK signal by the Memory Management Unit within a pre-fixed time has the following two implications.
First the MMU must be really able to answer within the pre-fixed time consistently with the read instruction received.
Second, once the DTACK signal has been generated, the read data must be really available with a delay not greater than a given value; that is, the duration of phases S3 and
This limitation should be usefully removed by allowing the memories (which can be of various types) to output valid data with different delays by lengthening phases S3 or S4.